RISC-V processors available today as physical Hardware
Many RISC-V processors designs exists like SiFive P870 or Codasips A730. But those are blue prints. In order to get a working computer on which software can be run, somebody has to integrate them into a SoC, have it manufactured, integrate the SoC into a board and have that manufactured as well.
As of today that number is far less. Some popular instances are shown in the table below. For reference there is also an ARM Design and x86 based design with a similar power envelope.
| Name | Hifive Premiere P550 | Banana Pi BPI-F3 | Framework Laptop StarFive VisionFive 2 |
Allwinner D1 | Lichee Pi 4A | Server SoC | Raspberry Pi 4 | Intel Atom |
|---|---|---|---|---|---|---|---|---|
| Architecture | RISC-V | RISC-V | RISC-V | RISC-V | RISC-V | RISC-V | ARM | x86 |
| Device Class | Single Board Computer | Single Board Computer | Laptop / Single Board Computer | Single Board Computer | Single Board Computer | Server SoC | Single Board Computer | Fanless |
| SoC | ESWIN EIC7700 | SpacemiT Keystone K1 | StarFive JH7110 | Allwinner D1 | Alibaba T-Head TH 1520 | Sophon SG2042 | Broadcom BCM2711 | Intel Pentium N6000 |
| Core | SiFive P550 | X60 | SiFive U74 | T-Head XuanTie C906 | T-Head XuanTie C910 | Alibaba T-Head XuanTie C920 | ARM Cortex A72 | Intel Tremont |
| Year of CPU Core IP Release | 2021 | 2024 | 2020 | 2020 | 2016 | 2019 | ||
| Year of Physical SoC Release | 2024 | 2024 | 2022 | 2021 | 2019 | 2021 | ||
| Stages | 13 | 8 | 8 | 5 | 12 | 12 | 15 | ~ 15 |
| OoO | Out of Order | In Order | In order | In Order | Out of Order | Out of Order | Out of Order | Out of Order |
| Issue width | 3 | 2 | 2 | 3 | 2+ | 3 | 10 | |
| # Cores | 4 Core | 8 Core | 4 Core | 4 Core | 64 Core | 4 Core | 4 Core | |
| L1$ | 32 KiB I, 32 KiB D | 32 KiB I, 32 KiB D | 32KiB I, 32 KiB D | 64 KiB I, 64 KiB D | 64 KiB I, 64 KiB D | 32 KiB I, 32 KiB D | ||
| L2$ | 256 KiB private | 1 MiB | 2 MiB shared | shared 2 MiB | shared 2 MiB per 4 core cluster | 1.5 MiB shared | ||
| L3$ | 4 MiB shared | - | - | 64 MiB | 4 MiB shared | |||
| Capabilities | RV64GBC | RVA22 | RV64GC | RV64GCV | RV64GC | RV64GCV | NEON, VFPv4 | SSE4 |
| Technology | 12 nm | ? | TSMC 28 nm | 22 nm | TSMC 12 nm | ? | Intel 10 | |
| Frequency | 1.8 GHz | 1.8 GHz | 1.5 GHz | 1 GHz | 1.8 GHz | 2 GHz | 1.5 GHz | 1.1 GHz (3.3 GHz) |
| Geekbench 5 SC | 195 (@1.8 GHz) | 84 @ 1.6 GHz | 74 @ 1.5 GHz | ? | ? | ? | 270 @1.8 GHz | 481 @ 1.1 GHz |
| Geekbench 5 SC / GHz | 108 | 52 | 49 | ? | ? | ? | 150 | 437 |
| Geekbench 5 MC | 700 (@1.8 GHz) | 514 | 263 | ? | ? | ? | 739 (@1.8 GHz) | 1106 |
Conclusions
A Raspberry Pi 4 from five years ago is 2 to 3 times faster than current RISC-V based offerings.
Likewise an Intel Atom processor from three years ago offers 4 to 8 times the performance.
Terminology
Technology refers to a specific manufacturing process of a specific foundry like TSMC, Samsung or Global Foundries. A smaller number indicates better transistors. This allows for more transistor per chip area and higher frequencies or lower power consumption.
Capabilities refers to standardized RISC-V extensions that the chip implements. A minimum set of required standardized extensions is referred to as a profile. These profiles include the most important extensions / instructions. The goal is to avoid fragmentation and ease software development for feature operating systems like Linux.
G is shorthand for M, A, F and D extensions:
M - Multiplication and Division
A - Atomic Memory Operations
F - single precision (32 bit) floating point
D - double precision (64 bit) floating point
The RVA22 profile additionally requires support for compressed instructions (16 bit compared to standard 32 bit) among other things.
Some of the cores also implement the following extensions:
B - Bit manipulation
V - Vector extension - one operation is performed on multiple data elements at a time. With the RVA23 profile and moving forward the vector extension will also be required.
Stages refers to the number of pipeline stages the core has. Instructions are not processed in a single cycle. Instead with each cycle they advance from one pipeline stage to the next. A classical pipeline would have the Fetch, Decode, Execute, Memory, Writeback stages. These can be further subdivided. Increasing the number of pipeline stages reduces the critical path and allows for higher frequencies and up to a point for higher performance.
OoO indicates whether the core is capable of processing instructions out-of-order. Software describes to the processor in what order to execute instructions. However that may result in an under-utilization of some functional units.
Out of order execution allows the core to change the execution order, while making sure that no data dependencies are violated. The results are then committed in order, as described by the software. For a given core microarchitecture, the out of order version will generally have better performance compared to the in-order variant.
Issue width refers to the maximum number of instructions that can begin execution in one cycle. A higher issue width allows for the extraction of instruction level parallelism and increases performance. A issue width of two allows a core to achieve up to two instructions per cycle, depending on data dependencies, cache misses, etc.