It happens not often that NASA switches to a new processor for their spacecraft. For example the rover Perseverance, which landed on Mars in 2021, uses for its processor the RAD750, developed some 30 years ago. Its based on a PowerPC 750, the one that was also used in the original iMac. Since then the hardware and software have proven themselves on many missions. However its compute performance, scalability, security and fault tolerance are lacking. In 2022 NASA awarded Microchip with a contract to design a new processor. Its to be used an all future lunar and planetary missions. The new processor should provide 100x the compute performance and also address the other needs. Recently Microchip announced that this processor is now being delivered. Its called PIC64-HPSC.

The main function blocks are depicted in the block diagram below:

It looks like a modern processor containing next to the CPU, memory and system controller a dedicated security coprocessor, lots of peripherals and an Ethernet Switch.

Processing Performance and Fault tolerance

The processing power is delivered by 8 SiFive X280 CPU Cores. The X280 is advertised with a compute performance of 4.6 Specint2k6 / GHz.

I'v tried to find ARM Cores with a similar Specint2k6 score. The closest one I found was a Cortex A75, estimated at 6.8 / Specint2k GHz.
Going by ARMs advertised generational performance gains of 20 % (A75 over A73) and 30 % (A73 over A72) and doing some crude math this would put the Cortex A72 at a similar performance level:

6.8 / (1.3 * 1.2) = 4.3 Specint2k6 / GHz

compared to SiFives X280. The Cortex A72 is used for example in the Raspberry Pi 4's Broadcom BCM2711 SoC. Given its similar performance and power level and popularity I thought the Pi 4 to be an interesting comparison point. Additionally its meant to highlight some space specific particularities of the PIC64, as the Pi is not build for space application but meant for teaching and sees some industrial applications.

The following table compares key specs of the Microchip PIC64 HPSC1000 with its predecessor the BAE RAD750 and the Raspberry Pi 4 SoC BCM2711.

Compared to recent x86 or ARM application class processors found in Laptops or Smartphones, SiFives X280 cores scalar processing capabilities are limited. Up to two instructions can be issued per cycle which are executed in order. In comparison even the Cortex A72 of the Raspi 4 are much more complex: capable of changing the instruction sequence to utilize the eight functional units as best as possible. What sets the X280 apart from many other core designs with similar scalar capabilities is the 512 bit long vectors with a true 512 bit data path. In comparison the Cortex A72 has smaller 128 bit vectors while the internal data path is only 64 bit. This means when using vector instructions, the per cycle throughput of an X280 core is 8 times higher compared to an Cortex A72. When using small numbers like INT8, which are typical for machine learning, up to 64 Multiply-Accumulate (MAC) operations can be performed by one 512-bit vector instruction.

On x86 512 bit vectors are part of the AVX512 instruction set extension. This can be found only in recent high performance µArch like Zen4/Zen5 and some Intel CPUs. Looking in the ARM world, 512 bit vectors are possible via the Scalable Vector Extensions (SVE). 512 bit vectors are used e.g. in Fugaku, worlds fastest supercomputer from 2020 to 2022 or Amazons data center processor Graviton3.

These vector processing capabilities allow the processor, which does not feature a dedicated Neural Processing Unit, to provide some reasonable throughput at advertised 2 TOPS. The TOPS number represents the theoretical maximum number of 8-bit-integer Multiply-Accumulate (MAC) operations that can be performed per second by all cores. A "G" refers to 10⁹ (Giga) or one billion, a "T" refers to 10¹² (Tera) or a trillion.
The OPS are the product of the number of cores, the frequency f and the number of 8 bit operations per vector. Although Multiply-Accumulate (MAC) is typically executed using just one instruction, its counted as two operations, hence the factor 2.

For comparison the latest iPhone 15 Pro features a dedicated NPU, capable of 35 TOPS, while Microsoft requires at least 40 TOPS for their "AI PCs".
The following table compares the performance of NASAs old and new processor as well as the P i4, using some popular CPU benchmarks where I could scores. Higher is better. Overall the performance uplift is substantial, achieving 65x the DMIPS score of previous processor. Compared to the ARM Cortex A72 cores in the Pi, the single core is worse, maybe half as good. The multicore performance seems on a similar level, thanks to having double the amount of cores.

*indicates own calculations based on reported scores

The CPU can be configured to run in lockstep, trading off half the CPU cores for increased fault tolerance, e.g. detection of single event upsets. With lockstep, a pair of CPUs executes the same code, with some cycles delay between them. When ever they come to different results, an error is raised and appropriate action can be taken. This can be as simple as running the code section again.

Next to the eight main CPU cores, there are two RISC-V cores embedded into the system and secure controller. Those are meant for house keeping tasks, freeing up the main CPU. This underscores the flexibility of the RISC-V architecture, being able to scale from simple embedded class cores to complex application class cores.
The secure controller acts as a platform root of trust. It supports secure boot. Additionally the post quantum cryptography protocols ML-KEM and ML-DSA are supported.

Scalability and Flexibility

Notable peripherals are CXL (Compute Express Link) TSN (Time Sensitive Networking). Those are relatively new standards, released only in the 2010s and 2020s, compared to I2C and SPI, released in the 1980s.

CXL was originally developed for high performance data center computers. It allows the host CPU and devices to work together in a shared coherent memory space. The coherency is managed by the CPU, enabling low latency and efficient memory access with a less compex software stack. Processing workloads can be more easily distributed between the CPU and accelerators (e.g. FPGA, GPU). This allows NASA to flexibly scale the performance of the computer as required by future missions.

TSN makes Ethernet based networks real-time capable. In contrast to Ethernet, there needs to be a guarantee that messages can be received within a certain maximum delay. This is important e.g. in control tasks like landing a spaceship where motors have to react to sensor input within a certain time frame, otherwise the spaceship will crash.

References

NASA Contract Announcement https://www.nasa.gov/news-release/nasa-awards-next-generation-spaceflight-computing-processor-contract/

Microchip PIC64 HPSC Announcement https://www.microchip.com/en-us/about/news-releases/products/microchip-unveils-industrys-highest-performance-64-bit-hpsc-mpu

SiFive X280 Specsheet https://sifive.cdn.prismic.io/sifive/9405d3d0-35a1-4680-a259-7a5598d1ecb2_sifive-intelligence-x200-datasheet.pdf

BAE RAD750 https://www.baesystems.com/en-media/uploadFile/20210404045936/1434555668211.pdf
http://powerpc.i-logout.cz/docs/rad750.pdf

Microchip PIC64 HPSC Series Specsheet https://ww1.microchip.com/downloads/aemDocuments/documents/MPU64/ProductDocuments/Brochures/PIC64-HPSC-Series-00005391.pdf